1. Field of the Invention
This invention relates to integrated circuits in general and, more particularly, to a bus with variable bandwidth in a system-on-a-chip.
2. Description of Related Art
Computer systems have traditionally comprised a system unit or housing which comprises a plurality of electrical components comprising the computer system. A computer system typically includes a motherboard, which is configured to hold the microprocessor and memory, and the one or more busses used in the computer system. The motherboard typically comprises a plurality of computer chips or electrical components including intelligent peripheral devices, bus controllers, processors, bus bridges, etc.
More recently, computer systems are evolving toward an integration of functions into a handful of computer chips. This coincides with the ability of chip makers to place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place up to ten million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place one billion transistors on a single chip. Thus, computer systems are evolving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. As a result, new architectures are necessary to take advantage of this increased integration. Therefore, an improved system is desired for information transfer between a plurality of different functions or modules on a single computer chip.
The problems outlined above are in large part solved an integrated circuit including a bus with variable clock rate in a system-on-a-chip. Broadly speaking, the integrated circuit includes at least one bus, a clock with a clock rate, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The bus operates at the clock rate, or a fraction or multiple thereof, of the clock. One or more of the plurality of modules is operable to generate requests to the bus controller to perform transfers on the bus.
In a preferred embodiment, each of the requests to perform data transfers comprise an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. In this embodiment, the bus controller receives the requests from one or more of the plurality of modules for data transfers among the plurality of modules, and, for each request, the bus controller analyzes the timing value provided with each request and selectively allocates bandwidth or adjusts the clock rate of the bus based on the timing value.
In another embodiment, the bus controller also examines the transfer size value, and further determines a minimum rate of transfer required to provide the bandwidth on the bus or a minimum clock rate for the clock required to meet the time frame within which the requested transfer should occur. The timing value may provide a definite time by which the data transfer must be completed for isochronous transfer or for guaranteed delivery. The timing value may also apply for voice, audio and/or video transfers.
In one embodiment, the integrated circuit further comprises a power control device coupled to or part of the bus controller, which monitors power consumption of the integrated circuit and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device.
In one embodiment, the bus is a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information. In various embodiments, the bus controller is operable to change the clock rate of the clock of the TDMA bus to conserve power in response to the power conservation information, such as slowing the clock rate of the TDMA bus to a slowest possible rate that meets the time frame of the timing value for the data transfer in response to the power conservation information. If the timing value indicates real-time or fast response, then the bus controller may assign multiple contiguous time slots to that data transfer associated with that request. Time slots may be set with any frequency and/or length, as desired.
In various embodiments, the bus controller includes, or has direct access to, a memory, which stores a schedule of the data transfers. The bus controller maintains the schedule based on the requests. The schedule includes information on time slot assignments for one or more of the plurality of modules. The bus controller examines the schedule when a new request is received and allocates unused time slots for the new request. The bus controller may adjust the schedule to allow a later request with a shorter timing value to receive an earlier time slot than previously scheduled requests. The previously scheduled requests are reassigned to later time slots, as necessary. The bus controller preferably receives multiple requests and determines time slot assignments that attempt to meet each request""s time frame. In one embodiment, the bus controller examines the priority value and the timing value when the bus controller analyzes the request for the transfer.